Reversible Circuit Synthesis Time Reduction Based on Subtree-Circuit Mapping
نویسندگان
چکیده
منابع مشابه
On the Synthesis of Sequential Reversible Circuit
Reversible circuits for SR ip op, JK ip op, D ip op, T ip op, Master Slave D ip op and Master Slave JK ip op have been provided with three di erent logical approaches. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule) and the optimized sequential circuits have been compared with the earlier propos...
متن کاملDepth-Optimized Reversible Circuit Synthesis
In this paper, simultaneous reduction of circuit depth and synthesis cost of reversible circuits in quantum technologies with limited interaction is addressed. We developed a cycle-based synthesis algorithm which uses negative controls and limited distance between gate lines. To improve circuit depth, a new parallel structure is introduced in which before synthesis a set of disjoint cycles are ...
متن کاملReversible Logic Circuit Based Twiddle Factor Generation
An efficient hardware implementation of FFT algorithm become essential one in signal analysis domain, more specifically the twiddle factor calculation in FFT computation plays important role in the speed and efficiency of the complete process. World of computation needs the fast and efficient tools to match the need of present scenario, even though there are many methods proposed the Reversible...
متن کاملA Novel Design of Reversible Multiplier Circuit (TECHNICAL NOTE)
Adders and multipliers are two main units of the computer arithmetic processors and play an important role in reversible computations. The binary multiplier consists of two main parts, the partial products generation circuit (PPGC) and the reversible parallel adders (RPA). This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced PPGC with Peres gates only. Ag...
متن کاملOptimized Reversible Multiplier Circuit
Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4× 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generaliz...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Applied Sciences
سال: 2020
ISSN: 2076-3417
DOI: 10.3390/app10124147